News digest of events from the FPGA / FPGA world - №005 (2020_09)

Beginners: Materials of the Skolkovo School of Digital Design are uploaded

From 15-17 September 2020, the SKOLKOVO SCHOOL OF SYNTHESIS OF DIGITAL SCHEMES ON VERILOG was held within the framework of the Chip-Expo exhibition. We are glad to announce that the materials of this school - the recording of video lectures and the source codes of the assignments - have been made publicly available on Youtube.

It is worth recalling that the proposal to get free debugging for schoolchildren and students to complete school is still valid.

Quartus Prime Pro Edition: Version 20.3 released

Intel FPGA  has released Quartus Prime Pro software update information. In particular, in the new version:

High-level FPGA programming for terabit communication lines

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: Enigma M3 FPGA Intel MAX10

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: Verification Day 2020

Synopsys  Verification Day 2020.  , , .

: RISC-V

Static Verification for RISC-V Cores and SoCs

—   RISC-V.

: PYNQ

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: FPGA Xilinx Production

Virtex UltraScale+ VU19P ASIC SoC, .  VU19P   - — FPGA - Xilinx....

: Xilinx FPGA - ST Micro

element14.com MicroBlaze — - Xilinx ST Micro. Arty-S7.

: RoE

Xilinx  --ethernet — Roe

Enhanced CPRI (eCPRI) 5G. IP Xilinx Radio over Ethernet Framer (RoE Framer) ...

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: 5

Silexica. John Inkeles 5 , HLS

: FPGA PCIe Gen5

Achronix , PCIe Gen5. , , .

: RISC-V UVM

Aldec Rivera-PRO  Codasip’s Studio RISC-V.

: Vivado , ()

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— Xilinx Vivado. Vivado , .

-: Xilinx Vitis

Vitis SoC Xilinx , . , Vitis Vitis AI.

FPGA M02mini marsohod.org

marsohod.org  FPGA M02mini Intel MAX10 10M02DCV36C8.

: HLS HDL ? ()

, HLS HDL. .

Cadence -

Cadence . Cadence   Cadence Support Account. 

: AES Verilog

medium.com

AES — 128 FPGA/ASIC Verilog.

: C Xilinx Zynq

hackster.io / Xilinx DDS Compiler + C+ baremetal + Zynq. ...

: Xilinx AI Engine MLIR

ACAP — Versal AI, . (02-02-2020), . , - ...

VUnit ()

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