Clever Geek Handbook

News digest of events from the FPGA / FPGA world - No. 0010 (2021_03) + FPGA developers conference

FPGA hi FPGA hub!







We continue to keep you updated with the latest developments in the world of programmable logic. Under the cut you will find fresh: articles, news, announcements, webinars, vacancies, and also information on the second national conference of FPGA developers











Webinars



  • Accelerate PCB Design with FPGAs Accelerating the PCB Design Process with FPGAs :

     , , . , , IC/ASIC .





  • Xilinx Versal ACAP in Russian Xilinx Versal ACAP ::

    ,  25--2021 2- Xilinx Versal ACAP. : C (@dsmv2011) (KeisN13) 





  • Increasing the productivity of RTL code verification in Matlab and Simulink RTL Matlab Simulink ::

    RTL FPGA ASIC .   , MATLAB / Simulink .





  • Plug & amp; Play FPGA programming for everyone Plug & Play FPGA ::

    IDE, . , FPGA .





    VHDPlus — FPGA. , ,





  • Webinar on Formal Verification of I / O Registers / ::

    , RTL, . , ? — Siemens.





  • SystemC and MatchLib Webinar SystemC MatchLib ::

    MatchLib SystemC , NVIDIA,





  • Bittware Intel OneAPI Webinar Intel OneAPI Bittware ::

    Intel  Bittware Intel oneAPI FPGA. 





    2D FFT, FPGA  520N-MX  Bittware.





  • Breaking into FPGA with Basys3 - workshop in two parts FPGA Basys3 — ::

    FPGA Xilinx. , FPGA, , Pong / Breakout. , Xilinx, Digilent Basys3.





  • Getting Started with Xilinx Versal ACAP Platform Xilinx Versal ACAP ::

    Xilinx -, Xilinx Customer Training Xilinx.









  • FPGA Developers for Onboard Systems: Aldec Adds 60+ New RTL Code Validation Rules FPGA : Aldec 60+ RTL- ::

    Aldec, Inc., VHDL/Verilog FPGA ASIC, 60 HDL DO-254 ALINT-PRO ( RTL)





  • AXI interconnect IP from TrueStream AXI interconnect IP TrueStream ::

    Truestream IP , AXI Intercinnect. IP — / N-to-1. .





  • Xilinx Returns to the Struggle for the Cost-Optimized Market Xilinx Cost-optimized ::

     eejournal.com , Xilinx UltraScale+ — Artix UltraScale+ Zynq ZU1. 





  • Artix UltraScale + and ZU1 Announcement Artix UltraScale+ ZU1 ::

    Xilinx UltraScale+ cost-optimized .   .











  • DSP on FPGA: A Simple FIR Filter on Veriog FPGA: Veriog ::

    . Whitney Knitter c hackster.io FPGA Verilog.





  • 10 Errors in FPGA Design 10 FPGA ::

     https://hardwarebee.com/ , 10 , FPGA . 





  • QuickLogic Re-Opens FPGA Design QuickLogic FPGA ::

    eejournal.com QuickLogic — ,   FPGA Arm Cortex-M4  QuickLogic EOS S3. 





  • Chisel training Chisel ::

    - chisel?   — . ?





  • So what exactly is FPGA? FPGA? ::

    HardwareBee.com ,   FPGA? FPGA ASIC, FPGA, FPGA CPLD, .





  • Implementing Triple Modular Redundancy (TMR) on MicroBlaze (TMR) MicroBlaze ::

    , 3 - MicroBlaze  Nexys 4 DDR FPGA (Xilinx Artix 7 FPGA) GPIO, IP- Triple Modular Redundancy (TMR)





  • Using the integrated logic analyzer (ila) and virtual I / O (vio) (ila) - (vio) ::

    vhdlwhiz.com Vivado: (ILA) / (VIO).





  • RISC-V Courses from The Linux Foundation RISC-V The Linux Foundation ::

     RISC-V International && The Linux Foundation





  • ::





  • Introduction to EDA Playground EDA Playground ::

    www.edaplayground.com, , .





  • What's new in VHDL 2019? VHDL 2019? ::

    , VHDL 2018: New and Noteworthy. DVCON 2018. VHDL 2019 , 2018 2019





  • Working asynchronously with libusb 1.0 libusb 1.0 ::

    USB- libusb. , , , , . ( ) . – .





  • Let's touch magic or how I joined the ranks of the MIST society MIST ::

    , 8 16- . miniMIG — Amiga core OCS/AGA/RTG CPU 68020 20 A600.























FPGA





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