News digest of events from the FPGA / FPGA world - No. 009 (2021_02) + FPGA conference

FPGA hi FPGA hub. 







We continue to keep you updated on the latest developments in the world of programmable logic and decided to slightly revise the digest format. We've added categories to make it easier to search. Under the cut you will find: articles, news, announcements, webinars, vacancies, and also information on the FPGA developers conference











Webinars



  • Quick start with Riviera-PRO FPGA simulator.  Part 1 - Project Input and Simulation Quick start with Riviera-PRO FPGA simulator. Part 1 - Project input and modeling :: This Thursday, February 25, at 17:00 Moscow time, a webinar for specialists in the design of FPGA code will take place ...
  • PLC2 Webinar: Low Power Real-Time Machine Vision and Artificial Intelligence Systems PLC2 Webinar: Low Power Real-Time Machine Vision and AI Systems :: FPGA - Why Does Architecture Matter? Are you a vision engineer or an artificial intelligence system designer? Surely you want to know why it is useful to use FPGAs or SoCs from Xilinx to solve your problems. ...
  • Functional verification of clock domain crossing (CDC) Functional Clock Domain Intersection Verification (CDC) :: ALINT-PRO provides powerful static analysis and validation of clock domain intersections (CDC). It extracts and validates clock trees and clock domains, applying topological pattern matching techniques to validate design structures at clock domain boundaries. However, static ...
  • Workshop Libero SoC Flash-FPGA Libero SoC Flash-FPGA :: , , , - . , 29 29 . , …
  • Webinar: Everything You Need to Know About Arrays in SystemVerilog : SystemVerilog :: Doulos Synopsys 10   «Everything You Need to Know about SystemVerilog Arrays». Synopsys VCS, …
  • RVfpga - microprocessor architecture course RVfpga — :: Imagination 2020- MIPSfpga.  Western Digital’s SweRV EH1 Core. …
  • FPGA Workshop FPGA :: ECE Department IIIT Delhi . MTech ECE, IIITD, Xilinx Vivado WebPack Edition.
  • Three Intel Agilex FPGA Webinars Intel Agilex FPGA :: Intel, , 10- Intel Agilex   .…




  • Xilinx Versal ACAP SmartLynq + Debug Module SmartLynq+ Versal ACAP Xilinx :: Xilinx , SmartLynq+. , , Versal, .…
  • SWA & nbsp; (single wire aggregation) - amazing, magical and amazing SWA  (single wire aggregation) — , :: . . «» - (GPIO) , …
  • Xilinx FPGA Playground Xilinx FPGA Playground :: , , ? ! Xilinx, Crowd Supply Digilent   Digilent Basys 3 FPGA Xilinx Artix-7,  WTFPGA, ,   - …
  • QuickSilicon invites you to participate in the hackathon QuickSilicon :: QuickSilicon . QuickSilicon , HDL, Verilog, SystemVerilog VHDL…
  • RV64X: Free Open Source RISC-V GPU RV64X: GPU RISC-V :: (GPU) RV64X RISC-V. , 3 . GPU FPGA ASIC.
  • GHDL 1.0.0 release GHDL 1.0.0 :: 20 GHDL ( FOSS VHDL,  )  1.0.0. GHDL — , , () VHDL. …




  • What to do when Zynq won't boot , Zynq :: , Zynq
  • Profiling an example of a neural network from the Vitis-AI repository on ZCU104 Vitis-AI ZCU104 :: Vitis-AI (#vitisai) «vaitrace».  https://youtu.be/vGu4aaXh6KA  . Vitis 2020.2 #ZCU104.…
  • Video review released: Programmer's Biblevhdl : VHDL ::    VHDL.   VHDL, VHDL…
  • Xilinx - Info Sheet # 01-2021 Xilinx — #01-2021 :: ! «» , , , . , …
  • HLS 300 MHz to RTL 500 MHz Kernel Conversion Guide for Vivado 2020.2 HLS 300 MHz RTL 500 MHz Vivado 2020.2 :: FPGA-Systems 2020 « RTL Vivado HLS kernel ALVEO» Vitis 2020.1. Vitis 2020.2 .
  • Development of a processor based on RISC-V architecture RISC-V :: , RISC-V, .    …






  • Gate Level FPGA-2 ::
  • SpinalHDL :: ? :: xHDL
  • UVM — Universal Verification Methodology FPGA
  • Embedded FPGA — Linux Zynq-7000






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FPGA/ — №008 (2021_01)







FPGA/ — №007 (2020_12)







FPGA/ — №006 (2020_10)







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