A free GPU that does not require royalties and there are no terms of use is a dream of many developers. Now a project is presented that is the beginning of a lot of work on creating fully open GPUs.
This is a project that is being developed by a group of enthusiasts together with Pixlica, the project itself is called RV64X. The main task of the team is to create an additional set of instructions for 3D graphics and multimedia data processing. The result should be a GPU that can be freely integrated into the processor based on the RISC-V architecture.
The project is based on vector instructions from the RISC-V ISA. They have been extended to support new data types and extensions that are specific to graphics processing. In particular, additional operations are proposed for processing pixels (RGBA), points (XYZW), texture elements (UVW-texels), vectors (operations with 2-4 vectors), material parameters, lighting calculation, transcendental mathematics, depth buffers (Z- buffer) and frame buffers (Framebuffer).
The first prototype, according to the developers, is designed for use only in microcontrollers, so its support is limited only to the Vulkan API. But over time, developers will add support for OpenGL and DirectX.
The idea behind the new project is the flexibility of the architecture, which allows you to connect extensions to solve various specific tasks, including two-phase truncation of cones, the use of fast Fourier transforms for arbitrary color depth and the implementation of hardware SLAM. The RV64X has the ability to implement its own stages for the computational pipeline, as well as geometric, pixel and frame buffers. The project also supports the creation of your own tessellators.
Manufacturers, using this project, have the opportunity to prepare chips designed for different tasks. At the same time, RV64X is the base.
The concept of the project is a hybrid CPU-GPU ISA, which allows you to create both specialized graphics microcontrollers and multi-core processors that combine computing cores with blocks to perform graphics operations. The processor integrated with the GPU will look like a single unit without the video block being allocated. It is programmed using a unified set of 64-bit instructions and a SIMD model to provide data-level parallelism.
We can also mention such a feature of the architecture of the new GPU as the use of a single memory model in both the CPU and the GPU, which makes it possible to do without additional RPC / IPC mechanisms for translating calls between the GPU memory and the CPU when processing 3D API operations. In this case, standard graphics operations can be implemented at the microcode level. Supports creating custom shaders, rasterizers and extensions for better tracing.
If necessary, developers can implement vector operations for working with simulation tasks, computer vision projects and machine learning.
As for the architecture implementation, it includes 32KB L1 cache for instructions and data, 8 KB of SRAM for microcode, an instruction decoder, a hardware implementation of RV32V and RV64X instruction sets, a microcode-specified extended instruction decoder, a vector arithmetic logic unit (ALU) , A 136-bit register file with 1,024 elements, a Special Function Unit (SFU), a Texture Unit, and a configurable local framebuffer.
