The M1 represents the beginning of a paradigm shift that will benefit the RISC-V microprocessors, but not in the way you think.
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loadi r3, 0 ; Load 0 into register r3
multiply:
add r3, r1 ; r3 ← r3 + r1
dec r2 ; r2 ← r2 - 1
bgt r2, multiply ; goto multiply if r2 > 0
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load r1, 84 ; get x-coordinate
loar r2, 85 ; get y-coordinate
DMA 110, 111 113, . , DMA:
loadi r1, 1024 ; set register r to source address
loadi r2, 50 ; bytes to copy
loadi r3, 2048 ; destination address
store r1, 110 ; tell DMA controller start address
store r2, 111 ; tell DMA to copy 50 bytes
store r3, 113 ; tell DMA where to copy 50 bytes to
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char *video_buffer = 0xB8000; // set pointer to CGA video buffer
video_buffer[3] = 42; // change color of 4th pixel
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RISC-V
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RISC-V Machine Learning Accelerator (ET-SOC-1)
Esperanto Technologies — , RISC-V. SoC ET-SOC-1, , SoC M1. 23,8 16 M1.
Firestorm , RISC-V ET-Maxion. , Linux. 1000 ET-Minion. RISC-V, RISC-V. ? , .
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ARM x86
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NVIDIA Jetson Nano.
RISC-V CPU?
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Intel RISC- 90-: Is It Game Over x86 ISA Intel?
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OTUS . . OTUS.
